1. Field of the Invention
The present invention relates to a structure of wirings or electrodes of a semiconductor device and a method of making thereof, and more particularly to a semiconductor device and a method of making thereof that accelerates the speed of a semiconductor device by reducing capacitances of wirings, and minimizes facilitating redundant process steps.
2. Description of the Related Art
Conventionally, polycrystal silicon including impurities in high concentration is used for a material of a gate electrode and wirings for connecting elements of a MOSFET constituting a semiconductor device. However, with the acceleration of the speed of a semiconductor device in recent years, a laminated structure of polycrystal silicon including impurities in high concentration and a metal having a low resistance and a high melting point or silicides thereof has been used more frequently than polycrystal silicon alone including impurities in high concentration.
FIGS. 1(a) and 1(b) illustrate a structure of a semiconductor device constituted by MOSFETs using the silicide technology.
FIG. 1(a) is a sectional view showing a semiconductor device manufactured by a conventional manufacturing method and FIG. 1(b) is a plan view of patterns of portions essential for facilitating understanding of the sectional view shown by FIG. 1(a). A section taken along a line I.sub.A --I.sub.A of FIG. 1(b) corresponds to FIG. 1(a).
With reference to FIG. 1(a), the semiconductor device includes a P-type silicon substrate 1, a P-type well 2, an N-type well 3 and an element isolating insulating layer 4. Further, in an order from the left in FIG. 1(a), a single PMOS (P-type Metal Oxide Semiconductor), a PMOS and an NMOS (N-type Metal Oxide Semiconductor) constituting a CMOS (Complementary Metal Oxide Semiconductor) inverter in which a gate electrode is integrally formed by a local wiring on the element isolating insulating layer (hereinafter, well isolating insulating layer) 4 on a boundary between the P-type well 2 and the N-type well 3, a single NMOS, a redundancy cut portion 15, and a wiring on the element separating insulating layer 4 and single body of NMOS on a P-type well, are formed.
Source and drain regions, gate electrodes and the like are connected to aluminum wirings 13 on an inter-layer insulating film 12 through contact holes.
According to the conventional method of making a semiconductor device as illustrated, the P-type well 2 and the N-type well 3 are formed on the substrate 1. Then, the element isolating insulating layer 4 is formed on the surface of the wells 2 and 3 by the LOCOS (Local Oxidation of Silicon) process or the STI (Shallow Trench Isolation) process. Next, thin thermally-oxidized films 5 as gate oxide films and polycrystal silicon portions 63 and 64 are successively formed. Next, the polycrystal silicon portions 63 and 64 are patterned by using lithography technology whereby gate electrodes and wirings are formed.
Next, N-regions 71 and P-regions 72 having a shallow diffusion depth are formed by ion-implanting impurities respectively into regions of the NMOSFET and the PMOSFET for forming sources and drains with the gate electrodes and a resist mask, not illustrated, serving as masks. Next, silicon nitride is formed all over the face and side walls 8 are formed on side faces of the gate electrodes by anisotropically etching silicon nitride. Next, impurities are again ion-implanted into regions for forming the sources and the drains with the gate electrodes formed with the side walls 8 and a resist mask, not illustrated, serving as masks. As a result, N+ regions 91 (source, drain regions) and P+ regions 92 (source, drain regions) having a deep diffusion depth are formed. Here, N- and P-designate low impurity concentration and N+ and P+ designate high impurity concentration.
Next, the gate insulating film 5 on the source and drain regions 91 and 92 of the N-type and the P-type MOSFETs, are removed and the respective source and drain regions 91 and 92 are exposed. Next, a high-melting point metal, for example, a titanium and a titanium nitride are continuously accumulated all over the face by a sputtering process. Next, heat treatment is carried out by which silicide layers 11 are formed. Unreacted titanium and titanium nitride are removed by etching.
The technology of forming a silicide layer self-aligningly on the surface of exposed silicon is referred to as SALICIDE (Self Aligned Silicide) technology.
Next, the inter-layer insulating film 12 is accumulated and the surface is flattened by a CMP (Chemical-Mechanical Polishing) process. Next, areas other than the openings of the contact holes are covered by a resist, not illustrated, and an anisotropic etching is carried out whereby a contact hole 19 extending toward the wiring and a contact hole 20 extending toward the diffusion layer are simultaneously opened. Thereafter, a high-melting point metal 18 such as tungsten or the like is selectively formed only at the opening portions of the contact holes 19 and 20 by using a CVD (Chemical Vapor Deposition) process. Next, the aluminum wirings 13 and a passivation film 14 are formed and the semiconductor device is completed after a pad step.
When the semiconductor device to be manufactured includes a memory, after the pad step, an etching is carried out on the passivation film 14 and the inter-layer insulating film 12 to a degree to form a shallow portion of the inter-layer insulating film 12 so that the redundancy cut portion 15 may be provided on the wiring comprising the polycrystal silicon portions 63 and the silicide layer 11 as shown by FIG. 1(a).
According to the conventional method of making the MOSFET, in the step of ion-implanting the regions for forming sources and drains, the gate electrodes and the wirings on the P-type well 2 and the gate electrodes and the wirings on the N-type well 3, are simultaneously ion-implanted.
Therefore, high concentrations of impurities are introduced into the polycrystal silicon portions 63 and 64 constituting the gate electrodes and the wirings, with the result that the gate electrodes and the wirings are formed to have high conductivity.
However, the following problems are caused when high concentrations of impurities are introduced into all of the polycrystal silicon portions.
That is, the wirings having constituent elements of the polycrystal silicon portions 63 and 64 which are formed on the element isolating insulating layer 4 and where high concentrations of impurities have been introduced, constitute the MIS (Metal Insulator Semiconductor) capacitance with respect to the surface of the wells via the element isolating insulating layer 4. The MIS capacitance has a very large value since it is formed between the lower faces of the polycrystal silicon portions 63 and 64 and the surface of the P-type well 2 or the surface of the N-type well 3. As a result, the capacitance of wirings is increased whereby high speed operation of the semiconductor device is hampered.
Further, when a voltage is applied on the wirings having the constituents of the polycrystal silicon portions 63 and 64, an inversion layer is caused in the P-type well 2 or the N-type well 3 beneath the element isolating insulating layer 4, whereby the function of the isolating elements may be lost.
Accordingly, the threshold voltage in causing such an inversion layer must be sufficiently higher than the operational voltage of the semiconductor device.
That is, in order to secure the function of isolating elements, the impurity concentration of the P-type well 2 and the N-type well 3 must be higher. However, thereby, the source-drain coupling capacitances that are formed between the source and the drain regions 91 and 92, and the P-type well 2 and the N-type well 3, are increased whereby high speed operation of the transistor is hampered.
Also, it is known that when high concentrations of impurities are introduced into polycrystal silicon, the formation of a silicide layer is hampered such that the formation of the silicide layer with a sufficient thickness becomes difficult. It is believed that impurities included in polycrystal silicon restrain a chemical reaction between polycrystal silicon and a high-melting point metal.
Therefore, even if the SALICIDE technology is used in the polycrystal silicon where high concentrations of impurities are introduced, the effect of reducing the sheet resistance of the wirings is restrained. Further, when design is advanced to achieve a finer structure and higher density of a semiconductor device and the width of wiring is narrowed, the effect of reducing the sheet resistance of wiring is further significantly restrained.
The sheet resistance is a resistance value per unit length in the unit wiring width which is used for evaluating the characteristic of wiring with .OMEGA./square as a unit.
Also, N-type impurities are introduced into gate electrodes and wirings of a MOSFET formed on a P-type well and P-type impurities are introduced into gate electrodes and wirings of a MOSFET formed on an N-type well to control the threshold value of the formed MOSFET. As illustrated by FIGS. 1(a) and 1(b), the N+ polycrystal silicon portion 63 and the P+ polycrystal silicon portion 64 produce a portion where they are brought into contact with each other on the well isolating insulating layer 4. The contact portion is electrically connected by the silicide layer 11 laminated on the polycrystal silicon portions 63 and 64.
However, in thermal steps of the manufacturing process, the impurities are mutually diffused from the P+ polycrystal silicon portion 64 to the N+ polycrystal silicon portion 63, or from the N+ polycrystal silicon portion 63 to the P+ polycrystal silicon portion 64 via the upper layer of the silicide layer 11 or directly. Therefore, the impurities of opposite conductive types may enter the gate electrodes of the P-type MOSFET and the N-type MOSFET which are integrally formed with the wirings and the threshold voltages of the respective FETs are varied such that an operational failure may be caused.
By flattening the inter-layer insulating film 12, the depth of the contact hole 19 extending toward the wiring, becomes smaller than the depth of the contact hole 20 extending toward the diffusing layer 91 by the amount of a sum of the stepwise differences of a portion of the layer 4 formed by LOCOS and the thickness of the wirings. In that case, when the contact hole 19 extending toward the wiring and the contact hole 20 extending toward the diffusion layer are simultaneously opened by etching according to the RIE (Reactive Ion Etching) process, the contact hole 19 extending toward the wiring is over-etched by a difference in the depths of both contact holes. Furthermore, when the film thickness of the silicide layer 11 which becomes a stopper of etching, is thin, or when morphology (flatness) is not excellent, the margin of the etching stopper is small and, accordingly, a portion of the silicide layer 11 of the opening portion of the contact hole 19 extending toward the wiring is lost, as shown in FIG. 1(a).
Even if a high-melting point metal such as tungsten or the like is selectively made to grow by the CVD (Chemical Vapor Deposition) process at the opening portion of the contact hole where a portion or all of the silicide layer 11 is lost, a sufficiently low resistance value is not provided in respect of contact with the wiring formed at the upper layer such that contact failure is caused.
In order to solve the problem, the contact hole 19 extending toward the wiring and the contact hole 20 extending toward the diffusion layer must be opened separately. However, this results in an increase in the number of process steps since the contact holes are opened twice.
Further, when a semiconductor device to be manufactured includes a memory, a memory cell that fails to operate is isolated by cutting the redundancy cut portion 15 illustrated by FIGS. 1(a) and 1(b), with the result that the formed memory including the defect is relieved. The cutting is carried out by thermally cutting and separating the wiring constituted by the polycrystal silicon portion 63 and the silicide layer 11 on the element isolating insulating layer 4, by using a laser machine device.
However, when the cutting of wiring is incomplete, for example, only the silicide layer 11 is cut, the polycrystal silicon portion 63 including a high concentration of impurities which is formed as a portion of the wiring, remains. Since the polycrystal silicon portion 63 has high conductivity, the wiring remains electrically connected whereby the rate of isolating memory cells from the redundancy portion is reduced.
As described above, according to the conventional technology, the polycrystal silicon portion where high concentrations of impurities are introduced, is constituted as the wiring. Therefore, the capacitance thereof with respect to the well regions is increased. Further, to secure the isolation characteristic of the element isolating insulating layer, the impurity concentration of the well must be increased whereby the coupling capacitance of the source and drain is increased. The high speed operation of the semiconductor device is hampered by these capacitances.
Further, it is difficult to form the silicide layer with a sufficient film thickness on the polycrystal silicon portion where high concentrations of impurities are introduced. Therefore, the effect of reducing the sheet resistance is decreased by forming a structure laminated with the silicide layer and the effect becomes significant with a finer structure of the semiconductor device.
Also, the polycrystal silicon portion where the impurities of opposite conductive types are introduced, is used on the P-type well and the N-type well. Therefore, there is a portion where the P+ polycrystal silicon portion and the N+ polycrystal silicon portion are brought into contact with each other. Therefore, the impurities are diffused into each other at the contact portion whereby the threshold voltage of the FET is varied, causing operational failure.
The depths of the contact hole extending toward the wiring and the contact hole extending toward the substrate are different and the margin of opening the contact hole extending toward the wiring is small. Accordingly, contact failure is apt to result. Also, the number of process steps is increased if the process is modified to prevent the contact failure on the local wiring of the polycrystal silicon portion.
Further, when the semiconductor device is formed to include a memory, if the cutting of wiring constituted by the polycrystal silicon portion is incomplete, the rate of isolating memory cells from the redundancy portion is low since the conductance of polycrystal silicon is high.
It is an object of the present invention to provide a semiconductor device and a method of making thereof for overcoming the above-described problems.